11.2.1 MAC Network Control Register
| Name: | MAC_NCR |
| Address: | 0x000 |
| Reset: | 0x00000000 |
| Property: | - |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | RO | RO | RO | RO | RO | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | R/W | R/W | R/W | R/W | R/W | WO | WO | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | R/W | R/W | WO | WO | WO | WO | WO | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| TXEN | RXEN | LBL | |||||||
| Access | R/W | WO | WO | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 3 – TXEN Transmit Enable
Writing a '1' to this bit enables the MAC transmitter to send data.
Writing a '0' to this bit stops transmission immediately, the transmit pipeline is cleared.
| Value | Description |
|---|---|
| 0 | Transmit is disabled |
| 1 | Transmit is enabled |
Bit 2 – RXEN Receive Enable
Writing a '1' to this bit enables the MAC to receive data.
Writing a '0' to this bit stops frame reception immediately, and the receive pipeline is cleared.
| Value | Description |
|---|---|
| 0 | Receive is disabled |
| 1 | Receive is enabled |
Bit 1 – LBL Loop Back Local
Writing '1' to this bit connects internal MII signals TXD[3:0] to RXD[3:0], TXEN to RXDV, and forces full duplex mode.
RXCK and TXCK to the internal PHY may malfunction as the MAC is switched into and out of internal loop back. It is important that receive and transmit circuits have already been disabled when making the switch into and out of internal loop back.
| Value | Description |
|---|---|
| 0 | Loop back local is disabled |
| 1 | Loop back local is enabled |