36.7.21 Pipe Interrupt Flag Set

Table 36-22. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Name:	PINTENSET - HOST_PIPE Mode
Offset:	0x109
Reset:	0x00
Property:	RW


Bit	7	6	5	4	3	2	1	0
			STALL	TXSTP	PERR	TRFAIL	TRCPT[1:0]
Access			RW	RW	RW	RW	RW	RW
Reset			0	0	0	0	0	0

Bit 5 – STALL Stall Interrupt Enable

Bit 4 – TXSTP Transmit Setup Interrupt Enable

Bit 3 – PERR Pipe Error Interrupt Enable

Bit 2 – TRFAIL Error Flow Interrupt Enable

Bits 1:0 – TRCPT[1:0] Transfer Complete x Interrupt Enable