36.7.20 End Point Interrupt Set Flag

Table 36-21. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Name:	EPINTENSET - DEVICE_ENDPOINT Mode
Offset:	0x109
Reset:	0x00
Property:	RW


Bit	7	6	5	4	3	2	1	0
		STALL[1:0]		RXSTP	TRFAIL[1:0]		TRCPT[1:0]
Access		RW	RW	RW	RW	RW	RW	RW
Reset		0	0	0	0	0	0	0

Bits 6:5 – STALL[1:0] Stall x In/out Interrupt enable

Bit 4 – RXSTP Received Setup Interrupt Enable

Bits 3:2 – TRFAIL[1:0] Error Flow x Interrupt Enable

Bits 1:0 – TRCPT[1:0] Transfer Complete x Interrupt Enable

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