36.7.4 Finite State Machine Status
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | FSMSTATUS |
| Offset: | 0x00D |
| Reset: | 0x01 |
| Property: | R |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| FSMSTATE[6:0] | |||||||||
| Access | R | R | R | R | R | R | R | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 1 | ||
Bits 6:0 – FSMSTATE[6:0] Fine State Machine Status
| Value | Name | Description |
|---|---|---|
| 0x1 | OFF | OFF (L3). It corresponds to the powered-off, disconnected, and disabled state |
| 0x2 | ON | ON (L0). It corresponds to the Idle and Active states |
| 0x4 | SUSPEND | SUSPEND (L2) |
| 0x8 | SLEEP | SLEEP (L1) |
| 0x10 | DNRESUME | DNRESUME. Down Stream Resume. |
| 0x20 | UPRESUME | UPRESUME. Up Stream Resume. |
| 0x40 | RESET | RESET. USB lines Reset. |