36.7.18 End Point Interrupt Clear Flag

Table 36-19. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Name:	EPINTENCLR - DEVICE_ENDPOINT Mode
Offset:	0x108
Reset:	0x00
Property:	RW


Bit	7	6	5	4	3	2	1	0
		STALL[1:0]		RXSTP	TRFAIL[1:0]		TRCPT[1:0]
Access		RW	RW	RW	RW	RW	RW	RW
Reset		0	0	0	0	0	0	0

Bits 6:5 – STALL[1:0] Stall x In/Out Interrupt Disable

Bit 4 – RXSTP Received Setup Interrupt Disable

Bits 3:2 – TRFAIL[1:0] Error Flow x Interrupt Disable

Bits 1:0 – TRCPT[1:0] Transfer Complete x Interrupt Disable

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.