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36.7.10 End Point Pipe Status Clear
Table 36-11. Register Bit Attribute
Legend Symbol Description Symbol Description Symbol Description R Readable bit HC Cleared by Hardware (Grey cell) Unimplemented W Writable bit HS Set by Hardware X Bit is unknown at Reset K Write to clear S Software settable bit — —
Name: EPSTATUSCLR - DEVICE_ENDPOINT Mode Offset: 0x104 Reset: 0x00 Property: W
Bit 7 6 5 4 3 2 1 0 BK1RDY BK0RDY STALLRQ[1:0] CURBK DTGLIN DTGLOUT Access W W W W W W W Reset 0 0 0 0 0 0 0
Bit 7 – BK1RDY Bank 1 Ready Clear
Bit 6 – BK0RDY Bank 0 Ready Clear
Bits 5:4 – STALLRQ[1:0] Stall x Request Clear
Bit 2 – CURBK Current Bank Clear
Bit 1 – DTGLIN Data Toggle IN Clear
Bit 0 – DTGLOUT Data Toggle OUT Clear
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