36.7.10 End Point Pipe Status Clear
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | EPSTATUSCLR - DEVICE_ENDPOINT Mode |
| Offset: | 0x104 |
| Reset: | 0x00 |
| Property: | W |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| BK1RDY | BK0RDY | STALLRQ[1:0] | CURBK | DTGLIN | DTGLOUT | ||||
| Access | W | W | W | W | W | W | W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||