32.8.119 Write Control Protection Register
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | WPCTRL |
| Offset: | 0x0030 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| WPKEY[23:16] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| WPKEY[15:8] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| WPKEY[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| WPLCK | WPEN | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 |
Bits 31:8 – WPKEY[23:0] Write Protection Key
Writing a value other than ETH_WPCTRL_KEY to this field cancels write operation to his register and generates a client bus error. This field always returns 0 on read.
Bit 1 – WPLCK Write Lock Bit
| Value | Description |
|---|---|
| 0 | WPCTRL is not write-protected. |
| 1 | WPCTRL register is write-protected. Non-debugger writes to this register are canceled and generate a client bus error. This bit can only be cleared by a hardware reset. |
Bit 0 – WPEN Write Protection Enable
| Value | Description |
|---|---|
| 0 | Register write protection disabled. |
| 1 | Register write protection enabled. Non-debugger writes to registers marked with write protection property are canceled and generate a client bus error. |