A read of this register returns the value
of the receive complete interrupt mask.
A write to this register directly affects
the state of the corresponding bit in the Interrupt Status Register, causing an
interrupt to be generated if a '1' is written.
The following values are valid for all
listed bit names of this register:
0: Corresponding interrupt is enabled.
1: Corresponding interrupt is
disabled.
Table 32-130. Register Bit Attribute
Legend| Symbol | Description | Symbol | Description | Symbol | Description |
|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
