32.8.10 GMAC Transmit Status Register

Table 32-25. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Name:	TSR
Offset:	0x1014
Reset:	0x00000000
Property:	-


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8
								HRESP
Access								R/W
Reset								0


Bit	7	6	5	4	3	2	1	0
	LCOL	UND	TXCOMP	TFC	TXGO	RLE	COL	UBR
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bit 8 – HRESP HRESP Not OK

Set when the DMA block sees HRESP not OK.

This bit is cleared by writing a '1' to it.

Bit 7 – LCOL Late Collision Occurred

This bit is only set if the condition occurs in gigabit mode, as retry is not attempted. Writing a one clears this bit.

Bit 6 – UND Transmit Underrun

This bit is set if the transmitter was forced to terminate a frame that it had already began transmitting due to further data being unavailable. This bit is set if a transmitter status write back has not completed when another status write back is attempted. When using the DMA interface configured for internal FIFO mode, this bit is also set when the transmit DMA has written the SOP data into the FIFO and either the AXI bus was not granted in time for further data, or because an AXI not OK response was returned, or because a used bit was read. When using the DMA interface configured for packet buffer mode, this bit will never be set.

Bit 5 – TXCOMP Transmit Complete

Set when a frame has been transmitted.

This bit is cleared by writing a '1' to it.

Bit 4 – TFC Transmit Frame Corruption Due to AXI Error

This bit is set when an error occurs during reading transmit frame from the AXI. Error causes include HRESP errors and buffers exhausted mid frame. (If the buffers run out during transmission of a frame then transmission stops, FCS shall be bad and GTXER asserted).

In DMA packet buffer mode, this bit is also set if a single frame is too large for the configured packet buffer memory size.

This bit is cleared by writing a '1' to it.

Bit 3 – TXGO Transmit Go

This bit is '1' when transmit is active. When using the DMA interface this bit represents the TXGO variable as specified in the transmit buffer description.