32.8.1 ETH Control A Register
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | CTRLA |
| Offset: | 0x0000 |
| Reset: | 0x00000000 |
| Property: | PAC Write Protected |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| RUNSTDBY | ENABLE | SWRST | |||||||
| Access | R/W | R/W | R/S/HC | ||||||
| Reset | 0 | 0 | 0 |
Bit 6 – RUNSTDBY Run in Standby
This bit is used to keep the ETH running in standby mode.
| Value | Description |
|---|---|
| 0 | The ETH module is disabled in Standby Sleep mode, clock requests are de-asserted after any pending bus transactions or requests are complete. |
| 1 | The ETH module continues to run in Standby Sleep mode. |
Bit 1 – ENABLE ETH Clock Enable
Changing the state of this bit from ‘0’ to ‘1’ or ‘1’ to ‘0’ sets the SYNCBUSY.ENABLE bit to 1. The SYNCBUSY.ENABLE bit stays asserted until the module is either completely enabled or completely disabled.
| Value | Description |
|---|---|
| 0 | Disable module. System clock is only requested for bus transactions. GCLK is never requested, turn off module, disable clocks, disable interrupt event generation. |
| 1 | Enable module by allowing both the generic clock and system clock requests based on the incoming clock requests. |
Bit 0 – SWRST Software Reset
The user should be able to reset the module independently of the different operating modes.
Writing a one to the SWRST bit resets the state of the module and all the registers.
The module will be disabled after the reset. When writing a one to SWRST, no other bits in this register will be written, as SWRST will clear all the bits in this register. After writing a one to SWRST bit, this bit will read back one until the module and the registers are reset. Any register write access during the ongoing reset will be discarded and an error will be generated. Read access can be performed without error generated and must return reset value. Writing a one to SWRST will have priority above all other actions, will always happen immediately and never stall the bus.
- Setting this bit also sets the SYNCBUSY.SWRST bit to 1. SYNCBUSY.SWRST bit stays 1 until reset sequence completes.
- Writing a zero to SWRST has no effect. User is expected to disable the module before it is reset. Due to synchronization there is a delay from writing CTRLA.SWRST until the reset is complete. CTRLA.SWRST and SYNCBUSY.SWRST will both be cleared when the reset is complete.
- During a SWRST, access to registers/bits without SWRST are disallowed until SYNCBUSY.SWRST is cleared by hardware.
| Value | Description |
|---|---|
| 0 | There is no reset operation ongoing |
| 1 | The reset operation is ongoing |