PIC32CZ CA80/CA90 Family

32.8.3 Event Control Register

Table 32-18. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Name:	EVCTRL
Offset:	0x000C
Reset:	0x00000000
Property:	PAC Write Protected, Enable Write-Protected


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8

Access
Reset


Bit	7	6	5	4	3	2	1	0
								CMPEO
Access								R/W
Reset								0

Bit 0 – CMPEO Enable the Output of the Time Stamp Compare Event

Value	Description
0	Not Enabled
1	Enabled

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