32.8.4 SYNCBUSY Register
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | SYNCB |
| Offset: | 0x0020 |
| Reset: | 0x00000000 |
| Property: | - |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ENABLE | SWRST | ||||||||
| Access | R/HS/HC | R/S/HC | |||||||
| Reset | 0 | 0 |
Bit 1 – ENABLE Module Enable Synchronization Busy
| Value | Description |
|---|---|
| 0 | Enable synchronization is not busy |
| 1 | Enable synchronization is busy |
Bit 0 – SWRST Software Reset Busy bit
Synchronizing Busy bit for CTRLA.SWRST
This bit is cleared when the synchronization of SWRST bit between the clock domains is complete.
This bit is set when the synchronization of SWRST bit between clock domains is started.
Note:
- When the CTRLA.SWRST is written, the user should poll SYNCB.SWRST bit to know when the reset operation is complete.
- During a SWRST, access to registers/bits without SWRST are disallowed until SYNCBUSY.SWRST is cleared by hardware.