32.8.17 GMAC Interrupt Mask Register
This register is a read-only register indicating which interrupts are masked. All bits are set at Reset and can be reset individually by writing to the Interrupt Enable Register (IER), or set individually by writing to the Interrupt Disable Register (IDR).
For test purposes there is a write-only function to this register that allows the bits in the Interrupt Status Register to be set or cleared, regardless of the state of the mask register. A write to this register directly affects the state of the corresponding bit in the Interrupt Status Register, causing an interrupt to be generated if a 1 is written.
The following values are valid for all listed bit names of this register when read:
0: The corresponding interrupt is enabled.
1: The corresponding interrupt is not enabled.
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | IMR |
| Offset: | 0x1030 |
| Reset: | 0x07FFFFFF |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| TSUTIMCMP | WOL | RXLPISBC | SRI | PDRSFT | PDRQFT | ||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 1 | 1 | 1 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| PDRSFR | PDRQFR | SFT | DRQFT | SFR | DRQFR | ||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 1 | 1 | 1 | 1 | 1 | 1 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| EXINT | PFTR | PTZ | PFNZ | HRESP | ROVR | ||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 1 | 1 | 1 | 1 | 1 | 1 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| TCOMP | TFC | RLEX | TUR | TXUBR | RXUBR | RCOMP | MFS | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
Bit 29 – TSUTIMCMP TSU Timer Comparison
Bit 28 – WOL Wake On LAN
Bit 27 – RXLPISBC Receive LPI indication Status Bit Change
Receive LPI indication status bit change.
Cleared on read.