57.3 Power Supply Specifications

Table 57-5. Power Supply Electrical Specifications
DC CHARACTERISTICS			Standard Operating Conditions: VDDIO = VDDIN 2.5V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
Param. No.	Symbol	Characteristics	Min.	Typ.	Max.	Units	Conditions
REG_1a	VDDCORE_CIN⁽³⁾	VDDCORE Input Bypass parallel Capacitor pair in single supply mode	—	100	—	nF	Ceramic XR7 with ESR <0.5Ω on all pins
REG_1b	VDDCORE_CIN⁽³⁾	VDDCORE Input Bypass parallel Capacitor pair in dual supply mode	—	4.7	—	µF	Bulk Ceramic or solid Tantalum with ESR <0.5Ω. Minimum and maximum represent absolute values including cap tolerances
REG_1b	VDDCORE_CIN⁽³⁾		—	100	—	nF	Ceramic XR7 with ESR <0.5Ω on all pins
REG_5	VDDIO_CIN⁽³⁾	VDDIO Input Bypass parallel Capacitor pair	—	4.7	—	µF	Bulk Ceramic or solid Tantalum with ESR <0.5Ω
REG_5	VDDIO_CIN⁽³⁾	VDDIO Input Bypass parallel Capacitor pair	—	100	—	nF	Ceramic XR7 with ESR <0.5Ω on all VDDIO pins
REG_9	VREFP_CIN⁽³⁾	External VREFP Input Bypass parallel Capacitor pair	—	1	—	µF	Bulk Ceramic or solid Tantalum with ESR <0.5Ω
REG_11	VDDPLLUSB_CIN⁽³⁾	USB PLL Power pin bypass capacitance	—	4.7	—	µF	Bulk Ceramic or solid Tantalum with ESR <0.5Ω
REG_11	VDDPLLUSB_CIN⁽³⁾	USB PLL Power pin bypass capacitance	—	100	—	nF	Ceramic XR7 with ESR <0.5Ω on all VDDIO pins
REG_13	VDDUTMII_CIN	USB Transceiver Power pin bypass capacitance	—	100	—	nF	Bulk Ceramic or solid Tantalum with ESR <0.5Ω
REG_13	VDDUTMII_CIN	USB Transceiver Power pin bypass capacitance	—	100	—	nF	Ceramic XR7 with ESR <0.5Ω on all VDDIO pins
REG_15	VDDUTMIC_CIN	USB Transceiver Core Power pin bypass capacitance	—	100	—	nF	Bulk Ceramic or solid Tantalum with ESR <0.5Ω
REG_15	VDDUTMIC_CIN	USB Transceiver Core Power pin bypass capacitance	—	100	—	nF	Ceramic XR7 with ESR <0.5Ω on all VDDIO pins
REG_17	VDDOUT_COUT⁽³⁾	VDDOUT Output Bypass parallel Capacitor pair in single supply mode	—	1	—	µF	Bulk Ceramic or solid Tantalum with ESR <0.5Ω
REG_17	VDDOUT_COUT⁽³⁾		—	100	—	nF	Ceramic XR7 with ESR <0.5Ω
REG_19	VDDPLL_CIN	VDD PLL Power pin bypass capacitance	—	100	—	nF	See Note 6
REG_19	VDDPLL_CIN	VDD PLL Power pin bypass capacitance	—	100	—	nF	See Note 6
REG_21	VDDIN_CIN⁽³⁾	VDDIN Input Bypass parallel Capacitor pair	—	4.7	—	µF	Bulk Ceramic or solid Tantalum with ESR <0.5Ω
REG_21	VDDIN_CIN⁽³⁾	VDDIN Input Bypass parallel Capacitor pair	—	100	—	nF	Ceramic XR7 with ESR <0.5Ω
REG_23	VDDIN_LEXT	VDDIN series Ferrite Bead DCR (DC Resistance)	—	—	0.15	Ω	≥600 Ohms @ 100 MHz
REG_23	VDDIN_LEXT	Ferrite Bead current Rating	500	—	—	mA	—
REG_27	VDDPLLUSB_LEXT	VDDIN series Ferrite Bead DCR (DC Resistance)	—	—	0.15	Ω	≥600 Ohms @ 100 MHz
REG_27	VDDPLLUSB_LEXT	Ferrite Bead current Rating	500	—	—	mA	—
REG_31	VDDCORE	Ferrite Bead current Rating	1.08	1.2	1.32	V	MCU Active, cache and prefetch disabled executing "while(1)" from Flash
REG_31A	IVDDCORE_MAX	VDDCORE max current	—	—	150	mA	LDO mode
REG_33	VDDIO ⁽²⁾	VDDIO Input Voltage Range	2.5	3.3	3.6	V	—
REG_34	VDDIN⁽²⁾	VDDIN Input Voltage Range	2.5	3.3	3.6	V	—
REG_35	VDDOUT	VDDOUT Output Voltage Range	1.2	1.23	1.26	V	Normal mode, ILOAD = 100 mA
REG_35b	IDDOUT	Max VDDOUT Output Current	—	—	150	mA	—
REG_36	VDDOUTON_TIME	VDDOUT Turn-on Time	—	1	2.5	ms	CDOUT = 1 μF, VDDOUT reaches DC output voltage
REG_37	VDDPLL	Main Oscillator Supply	VDDCORE	—	VDDCORE	V	—
REG_38	VDDUTMIC	DC Supply UDPHS and UHPHS UTMI+ Core	1.08	1.2	1.32	V	—
REG_39	VDDUTMII	DC Supply UDPHS and UHPHS UTMI+ Interface	3	3.3	3.6	V	—
REG_40	VDDPLLUSB	UTMI PLL Supply	3	3.3	3.6	V	—
REG_41	SVDDCORE_R	VDDCORE Rise Ramp Rate	1.2	—	30	V/ms	Failure to meet this specification may lead to start-up or unexpected behaviors
REG_43	SVDDIO_R	VDDIO Rise Ramp Rate to Ensure Internal Power-on Reset Signal	1.9	—	30	V/ms	Failure to meet this specification may lead to start-up or unexpected behaviors
REG_44	SVDDIO_F	VDDIO Falling Ramp Rate to Ensure Internal Power-on Reset Signal	1.9	—	30	V/µs	Failure to meet this specification may cause the device to not detect reset
REG_45a	VPOR	VDDIO Power-on Reset	1.37	—	1.61	V	VDDIO Power up/Power down (See Param REG43, VDDIO Ramp Rate)
REG_45b	VPOR_CORE	VDDCORE Power-on Reset	0.66	—	1.07	V	—
REG_53	TRST	External RESET valid active pulse width	94 (3*SLCK cycles)	—	—	µs	Minimum reset active time to guarantee MCU reset
REG_55	VPOR_HYS	VDDIO POR Hysteresis Voltage	40	80	130	mV	—
REG_59	VPOR_HYS_CORE	VDDCORE POR Hysteresis Voltage	10	60	115	mV	—
REG_63	VBOD_THR	Core Supply Brownout Falling Threshold	0.97	1	1.04	V	—
REG_65	VBOD_HYS	Hysteresis Voltage	—	25	50	mV	—
REG_69	VMON_THR	VDDIO Supply Monitor Threshold	—	2.56	—	V	Digital Code 1000
			—	2.68	—	V	Digital Code 1001
			—	2.8	—	V	Digital Code 1010
			—	2.92	—	V	Digital Code 1011
			—	3.04	—	V	Digital Code 1100
			—	3.16	—	V	Digital Code 1101
			—	3.28	—	V	Digital Code 1110
			—	3.4	—	V	Digital Code 1111
REG_71	VMON_ACC	Supply Monitor Threshold Accuracy	-4	—	4	%	—
REG_73	VMON_HYS	Supply Monitor Hysteresis Voltage	—	38	45	mV	—
REG_74	R-VBG	External Pull-Down Resistor recommended on VBG pin	—	5620	—	Ω	Resistor value tolerance: +/-1%
REG_75	C-VBG	External Decoupling Capacitor recommended on VBG pin	—	10	—	pF	—
Note: Ferrite Bead ISAT(min) ≥ (IDDANA(max) * 1.15). VDDIO and VDDIN must be at the same voltage level. All bypass caps must be located immediately adjacent to pins and on the same side of the PCB as the MCU.

PIC32CZ CA70/MC70

57.3 Power Supply Specifications