3.4.4.5.1 Buffer Slice Architecture

  • Address valid register
    • Indicates that a valid address has been stored in all ISB slice address registers - FIFO head address, SSA address, etc., preventing a false hit coming out of Reset. Keeps ISB from thrashing in multiple loop scenarios. The same buffer slices are used in the repetitive loop.
  • Stream start address register (SSA)
    • Stores the start address of an instruction stream. The SSA address stays the same as the FIFO head address changes [(ADDR_WIDTH-1):4].
  • FIFO head address register. This is compared to the CPU address to generate a hit signal. The FIFO head address is incremented under two scenarios.
  • NVM prefetch address register
  • Address comparators
  • ISB data FIFO
  • ISB prefetcher - tracks where the data needs to go - status bit appended to each FIFO - each FIFO must set a status bit - there should be only one assignment bit set indicating where NVM read data should go. NVM can latch 2 addresses at a time. Time is needed for ECC calculation, so it can take a new address in the third cycle and start the next fetch. There are only two PF bits per slice because two fetches can be pending from Flash at any given time. These bits indicate where the first fetch and second fetch go.
  • LRU register
  • BTIC second word flag
  • ISB slice error register - BTIC mode - BTIC loads from cache to ISB with parity error
  • Prefetch-N counter
Figure 3-23. Instruction Stream Buffer - One Slice
Note: Any of the 32-bit instructions shown could also be a pair of 16-bit instructions, allowing up to 8 instructions per 128-bit program word.