3.5.21 Modulo and Bit-Reversed Addressing Control Register
| Name: | MODCON |
| Offset: | 0x46 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| XMODEN | YMODEN | BWM[3:0] | |||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| YWM[3:0] | XWM[3:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 15 – XMODEN X RAGU and X WAGU Modulus Addressing Enable bit
| Value | Description |
|---|---|
| 1 | X AGU Modulus Addressing enabled. |
| 0 | X AGU Modulus Addressing disabled. |
Bit 14 – YMODEN Y AGU Modulus Addressing Enable bit
| Value | Description |
|---|---|
| 1 | Y AGU Modulus Addressing enabled. |
| 0 | Y AGU Modulus Addressing disabled. |
Bits 11:8 – BWM[3:0] X WAGU Register Select for Bit-Reversed Addressing bits
| Value | Description |
|---|---|
| 1111 | W15 Bit-Reversed Addressing disabled. |
| 1110 | W14 selected for Bit-Reversed Addressing. |
| 0000 | W0 selected for Bit-Reversed Addressing. |
Bits 7:4 – YWM[3:0] Y AGU W Register Select for Modulo Addressing bits
| Value | Description |
|---|---|
| 1111 | W15 Bit-Reversed Addressing disabled. |
| 1110 | W14 selected for Bit-Reversed Addressing. |
| 0000 | W0 selected for Bit-Reversed Addressing. |
Bits 3:0 – XWM[3:0] X RAGU and X WAGU W Register Select for Modulo Addressing bits
| Value | Description |
|---|---|
| 1111 | W15 Bit-Reversed Addressing disabled. |
| 1110 | W14 selected for Bit-Reversed Addressing. |
| 0000 | W0 selected for Bit-Reversed Addressing. |