3.5.19 CPU STATUS Register
- The IPL[2:0] bits are concatenated with the IPL[3] bit
(CORCON[3]) to form the CPU Interrupt Priority Level. The value in parentheses
indicates the IPL, if IPL[3] =
1. User interrupts are disabled when IPL[3] =1. - The IPL[2:0] Status bits are read-only when the NSTDIS bit
(INTCON1[15]) =
1. - A data write to the SR register can modify the SA and SB bits by either a data write to SA and SB or by clearing the SAB bit. To avoid a possible SA or SB bit write race condition, the SA and SB bits should not be modified using bit operations.
Legend: C = Clearable bit
| Name: | SR |
| Offset: | 0x42 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| OA | OB | SA | SB | OAB | SAB | DA | DC | ||
| Access | R/W | R/W | R/W | R/W | R/C | R/C | R | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| IPL[2:0] | RA | N | OV | Z | C | ||||
| Access | R/W | R/W | R/W | R | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 15 – OA Accumulator A Overflow Status bit
| Value | Description |
|---|---|
1 |
Accumulator A has overflowed |
0 |
Accumulator A has not overflowed |
Bit 14 – OB Accumulator B Overflow Status bit
| Value | Description |
|---|---|
1 |
Accumulator B has overflowed. |
0 |
Accumulator B has not overflowed. |
Bit 13 – SA Accumulator A Saturation ‘Sticky’ Status bit(3)
| Value | Description |
|---|---|
1 |
Accumulator A is saturated or has been saturated at some time. |
0 |
Accumulator A is not saturated. |
Bit 12 – SB Accumulator B Saturation ‘Sticky’ Status bit(3)
| Value | Description |
|---|---|
1 |
Accumulator B is saturated or has been saturated at some time. |
0 |
Accumulator B is not saturated. |
Bit 11 – OAB OA || OB Combined Accumulator Overflow Status bit
| Value | Description |
|---|---|
1 |
Accumulator A or B has overflowed. |
0 |
Neither Accumulator A or B has overflowed. |
Bit 10 – SAB SA || SB Combined Accumulator ‘Sticky’ Status bit
| Value | Description |
|---|---|
1 |
Accumulator A or B is saturated or has been saturated at some time. |
0 |
Neither Accumulator A or B is saturated. |
Bit 9 – DA
DO Loop Active bit
| Value | Description |
|---|---|
1 |
|
0 |
|
Bit 8 – DC MCU ALU Half Carry/Borrow bit
| Value | Description |
|---|---|
1 |
A carry-out from the fourth low-order bit (for byte-sized data) or eighth low-order bit (for word-sized data) of the result occurred. |
0 |
No carry-out from the fourth low-order bit (for byte-sized data) or eighth low-order bit (for word-sized data) of the result occurred. |
Bits 7:5 – IPL[2:0] CPU Interrupt Priority Level Status bits(1,2)
| Value | Description |
|---|---|
111 |
CPU Interrupt Priority Level is 7 (15); user interrupts are disabled. |
110 |
CPU Interrupt Priority Level is 6 (14). |
101 |
CPU Interrupt Priority Level is 5 (13). |
100 |
CPU Interrupt Priority Level is 4 (12). |
011 |
CPU Interrupt Priority Level is 3 (11). |
010 |
CPU Interrupt Priority Level is 2 (10). |
001 |
CPU Interrupt Priority Level is 1 (9). |
000 |
CPU Interrupt Priority Level is 0 (8). |
Bit 4 – RA
REPEAT Loop Active bit
| Value | Description |
|---|---|
1 |
|
0 |
|
Bit 3 – N MCU ALU Negative bit
| Value | Description |
|---|---|
1 |
Result was negative. |
0 |
Result was non-negative (zero or positive). |
Bit 2 – OV MCU ALU Overflow bit
This bit is used for signed arithmetic (two’s complement). It indicates an overflow of the magnitude that causes the sign bit to change state.
| Value | Description |
|---|---|
1 |
Overflow occurred for signed arithmetic (in this arithmetic operation). |
0 |
No overflow occurred. |
Bit 1 – Z MCU ALU Zero bit
| Value | Description |
|---|---|
1 |
An operation that affects the Z bit has set it at some time in the past. |
0 |
The most recent operation that affects the Z bit has cleared it (i.e., a non-zero result). |
Bit 0 – C MCU ALU Carry/Borrow bit
| Value | Description |
|---|---|
1 |
A carry-out from the Most Significant bit of the result occurred. |
0 |
No carry-out from the Most Significant bit of the result occurred. |