3.5.30 EDS Bus Master Priority Control Register
| Name: | MSTRPR |
| Offset: | 0x58 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DMAPR | CANPR | NVMPR | |||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 |
Bit 5 – DMAPR Modify DMA Controller Bus Main Priority Relative to CPU bit
| Value | Description |
|---|---|
| 1 | Raises the DMA Controller bus main priority above that of the CPU. |
| 0 | No change to the DMA Controller bus main priority. |
Bit 4 – CANPR Modify CAN1 Bus Main Priority Relative to CPU bit
| Value | Description |
|---|---|
| 1 | Raises the CAN1 bus main priority above that of the CPU. |
| 0 | No change to the CAN1 bus main priority. |
Bit 0 – NVMPR Modify NVM Controller Bus Main Priority Relative to CPU bit
| Value | Description |
|---|---|
| 1 | Raises the NVM Controller bus main priority above that of the CPU. |
| 0 | No change to the NVM Controller bus main priority. |