15.5.4 UARTx Status Register High
- The receive watermark interrupt is not set if PERIF or FERIF is set and the corresponding IE bit is set.
Legend: S = Settable bit, HS = Hardware Settable bit
| Name: | UxSTAH |
| Offset: | 0x23E, 0x266, 0xF06 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| UTXISEL[2:0] | URXISEL[2:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| TXWRE | STPMD | UTXBE | UTXBF | RIDLE | XON | URXBE | URXBF | ||
| Access | R/W/HS | R/W | R/S | R | R | R | R/S | R | |
| Reset | 0 | 0 | 1 | 0 | 1 | 1 | 1 | 0 |
Bits 14:12 – UTXISEL[2:0] UART Transmit Interrupt Select bits
| Value | Description |
|---|---|
111 |
Sets transmit interrupt when there is one empty slot left in the buffer. |
| . . . | |
010 |
Sets transmit interrupt when there are six or more empty slots in the buffer. |
001 |
Sets transmit interrupt when there are seven or more empty slots in the buffer. |
000 |
Sets transmit interrupt when there are eight or more empty slots in the buffer; TX buffer is empty. |
Bits 10:8 – URXISEL[2:0] UART Receive Interrupt Select bits(1)
| Value | Description |
|---|---|
111 |
Triggers receive interrupt when there are eight words in the buffer; RX buffer is full. |
| . . . | |
001 |
Triggers receive interrupt when there are two or more words in the buffer. |
000 |
Triggers receive interrupt when there is one or more words in the buffer. |
Bit 7 – TXWRE TX Write Transmit Error Status bit
LIN and Parity Modes:
1 = A new byte was written when buffer was full or when P2[8:0] =
0 (must be cleared by software).
0 = No error.
Address Detect Mode:
1 = A new byte was written when buffer was full or to P1[8:0] when
P1x was full (must be cleared by software).
0 = No error.
Other Modes:
1 = A new byte was written when buffer was full (must be cleared by
software).
0 = No error.
Bit 6 – STPMD Stop Bit Detection Mode bit
| Value | Description |
|---|---|
1 |
Triggers RXIF at the end of the last Stop bit. |
0 |
Triggers RXIF in the middle of the first (or second, depending on the STSEL[1:0] setting) Stop bit. |
Bit 5 – UTXBE UART TX Buffer Empty Status bit
| Value | Description |
|---|---|
1 |
Transmit buffer is empty; writing ‘ |
0 |
Transmit buffer is not empty. |
Bit 4 – UTXBF UART TX Buffer Full Status bit
| Value | Description |
|---|---|
1 |
Transmit buffer is full. |
0 |
Transmit buffer is not full. |
Bit 3 – RIDLE Receive Idle bit
| Value | Description |
|---|---|
1 |
UART RX line is in the Idle state. |
0 |
UART RX line is receiving something. |
Bit 2 – XON UART in XON Mode bit
Only valid when FLO[1:0] control bits are set to XON/XOFF mode.
| Value | Description |
|---|---|
1 |
UART has received XON. |
0 |
UART has not received XON or XOFF was received. |
Bit 1 – URXBE UART RX Buffer Empty Status bit
| Value | Description |
|---|---|
1 |
Receive buffer is empty; writing ‘ |
0 |
Receive buffer is not empty. |
Bit 0 – URXBF UART RX Buffer Full Status bit
| Value | Description |
|---|---|
1 |
Receive buffer is full. |
0 |
Receive buffer is not full. |