17.3 Secondary Address Masking

The I2C1MSK register (I2C1MSK) designates address bit positions as “don’t care” for both 7-Bit and 10-Bit Addressing modes. Setting a particular bit location (= 1) in the I2C1MSK register causes the Secondary module to respond, whether the corresponding address bit value is a ‘0’ or a ‘1’. For example, when I2C1MSK is set to ‘0010000000’, the Secondary module will detect both addresses, ‘0000000000’ and ‘0010000000’.

To enable address masking, the Intelligent Peripheral Management Interface (IPMI) must be disabled by clearing the STRICT bit (I2CxCONL[11]).

Note: As a result of changes in the I²C protocol, the addresses in Table 17-2 are reserved and will not be Acknowledged in Secondary mode. This includes any address mask settings that include any of these addresses.

Table 17-1. I2Cx Clock Rates^(1,2)
F_CY	F_SCL	I2CxBRG Value
F_CY	F_SCL	Decimal	Hexadecimal
100 MHz	1 MHz	41	29
100 MHz	400 kHz	116	74
100 MHz	100 kHz	491	1EB
80 MHz	1 MHz	32	20
80 MHz	400 kHz	92	5C
80 MHz	100 kHz	392	188
60 MHz	1 MHz	24	18
60 MHz	400 kHz	69	45
60 MHz	100 kHz	294	126
40 MHz	1 MHz	15	0F
40 MHz	400 kHz	45	2D
40 MHz	100 kHz	195	C3
20 MHz	1 MHz	7	7
20 MHz	400 kHz	22	16
20 MHz	100 kHz	97	61
Note: Based on F_CY = F_OSC/2; Doze mode and PLL are disabled. These clock rate values are for guidance only. The actual clock rate can be affected by various  system-level parameters. The actual clock rate should be measured in its intended application.

Table 17-2. I2Cx Reserved Addresses⁽¹⁾
Secondary Address	R/W Bit	Description
`0000 000`	`0`	General Call Address⁽²⁾
`0000 000`	`1`	Start Byte
`0000 001`	`x`	Cbus Address
`0000 01x`	`x`	Reserved
`0000 1xx`	`x`	HS Mode Host Code
`1111 0xx`	`x`	10-Bit Client Upper Byte⁽³⁾
`1111 1xx`	`x`	Reserved
Note: The address bits listed here will never cause an address match independent of address mask settings. This address will be Acknowledged only if GCEN = `1`. A match on this address can only occur on the upper byte in 10-Bit Addressing mode.