3.6.5 Floating-Point Control Register
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Floating-Point Exception Mask bits, FCR [6:0]: Each Exception Mask bit corresponds to an Exception Status flag in the FSR. The Mask bit must be clear to allow the exception event to generate an interrupt to the CPU. The Underflow Mask bit (FCR.UDFM) is also used as part of the Flush-to-Zero (FTZ) mode enable as discussed in Flush-To-Zero (FTZ).
Floating-point rounding mode control, FCR [9:8]: These bits define the global IEEE 754 compatible rounding mode used by the FPU instruction. See Rounding Modes.
Floating-point subnormal override mode control, FCR [11:10]: These bits enable the Subnormals-Are-Zero (SAZ) and Flush-To-Zero (FTZ) subnormal override modes supported by the FPU.
| Name: | FCR |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| SAZ | FTZ | RND [1:0] | |||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SUBOM | HUGIM | INXM | UDFM | OVFM | DIV0M | INVALM | |||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 11 – SAZ Subnormals-Are-Zero Operand Mode bit
| Value | Description |
|---|---|
| 1 | Subnormals-Are-Zero mode is enabled. |
| 0 | Subnormals-Are-Zero mode is disabled. |
Bit 10 – FTZ Flush-To-Zero Result Mode bit
| Value | Description |
|---|---|
| 1 | Flush-To-Zero mode is enabled. |
| 0 | Flush-To-Zero mode is disabled. |
Bits 9:8 – RND [1:0] FPU Rounding Mode bits
| Value | Description |
|---|---|
| 11 | IEEE Round to Negative Infinity (floor) |
| 10 | IEEE Round to Positive Infinity (ceiling) |
| 01 | IEEE Round to Zero (truncate) |
| 00 | IEEE Round to Nearest (even) |
Bit 6 – SUBOM Subnormal Operand Exception Mask bit
| Value | Description |
|---|---|
| 1 | Subnormal exception is masked. |
| 0 | Subnormal exception is not masked. |
Bit 5 – HUGIM Huge Integer Exception Mask bit
| Value | Description |
|---|---|
| 1 | Huge Integer exception is masked. |
| 0 | Huge Integer exception is not masked. |
Bit 4 – INXM Inexact Exception Mask bit
| Value | Description |
|---|---|
| 1 | Inexact exception is masked. |
| 0 | Inexact exception is not masked. |
Bit 3 – UDFM Underflow Exception Mask bit
| Value | Description |
|---|---|
| 1 | Underflow exception is masked. |
| 0 | Underflow exception is not masked. |
Bit 2 – OVFM Overflow Exception Mask bit
| Value | Description |
|---|---|
| 1 | Overflow exception is masked. |
| 0 | Overflow exception is not masked. |
Bit 1 – DIV0M Divide-By-Zero Exception Mask bit
| Value | Description |
|---|---|
| 1 | Divide-By-Zero exception is masked. |
| 0 | Divide-By-Zero exception is not masked. |
Bit 0 – INVALM Invalid Exception Mask bit
| Value | Description |
|---|---|
| 1 | Invalid exception is masked. |
| 0 | Invalid exception is not masked. |