21.3.6 SPIx Interrupt Mask Register
- Mask values higher than Value 4 are not valid. The module will not trigger a match for any value in this case.
Legend: R = Readable bit, W = Writable bit
| Name: | SPIxIMSK |
| Offset: | 0x1814, 0x1834, 0x1854, 0x1874 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| RXWIEN | RXMSK[2:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| TXWIEN | TXMSK[2:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| FRMERREN | BUSYEN | SPITUREN | |||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SRMTEN | SPIROVEN | SPIRBEN | SPITBEN | SPITBFEN | SPIRBFEN | ||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 31 – RXWIEN Receive Watermark Interrupt Enable bit
| Value | Description |
|---|---|
1 |
Triggers receive buffer element watermark interrupt when RXMSK[2:0] ≤ RXELM[2:0]. |
0 |
Disables receive buffer element watermark interrupt. |
Bits 26:24 – RXMSK[2:0] RX Buffer Mask bits(1)
RX mask bits; used in conjunction with the RXWIEN bit.
Bit 23 – TXWIEN Transmit Watermark Interrupt Enable bit
| Value | Description |
|---|---|
1 |
Triggers transmit buffer element watermark interrupt when TXMSK[2:0] ≤ TXELM[2:0]. |
0 |
Disables transmit buffer element watermark interrupt. |
Bits 18:16 – TXMSK[2:0] TX Buffer Mask bits(1)
TX mask bits; used in conjunction with the TXWIEN bit.
Bit 12 – FRMERREN Enable Interrupt Events via FRMERR bit
| Value | Description |
|---|---|
1 |
Frame error generates an interrupt event. |
0 |
Frame error does not generate an interrupt event. |
Bit 11 – BUSYEN Enable Interrupt Events via SPIBUSY bit
| Value | Description |
|---|---|
1 |
BUSY generates an interrupt event. |
0 |
BUSY does not generate an interrupt event. |
Bit 8 – SPITUREN Enable Interrupt Events via SPITUR bit
| Value | Description |
|---|---|
1 |
Transmit Underrun (TUR) generates an interrupt event. |
0 |
Transmit Underrun does not generate an interrupt event. |
Bit 7 – SRMTEN Enable Interrupt Events via SRMT bit
| Value | Description |
|---|---|
1 |
Shift Register Empty (SRMT) generates interrupt events. |
0 |
Shift Register Empty does not generate interrupt events. |
Bit 6 – SPIROVEN Enable Interrupt Events via SPIROV bit
| Value | Description |
|---|---|
1 |
SPIx Receive Overflow (ROV) generates an interrupt event. |
0 |
SPIx Receive Overflow does not generate an interrupt event. |
Bit 5 – SPIRBEN Enable Interrupt Events via SPIRBE bit
| Value | Description |
|---|---|
1 |
SPIx RX buffer empty generates an interrupt event. |
0 |
SPIx RX buffer empty does not generate an interrupt event. |
Bit 3 – SPITBEN Enable Interrupt Events via SPITBE bit
| Value | Description |
|---|---|
1 |
SPIx transmit buffer empty generates an interrupt event. |
0 |
SPIx transmit buffer empty does not generate an interrupt event. |
Bit 1 – SPITBFEN Enable Interrupt Events via SPITBF bit
| Value | Description |
|---|---|
1 |
SPIx transmit buffer full generates an interrupt event. |
0 |
SPIx transmit buffer full does not generate an interrupt event. |
Bit 0 – SPIRBFEN Enable Interrupt Events via SPIRBF bit
| Value | Description |
|---|---|
1 |
SPIx receive buffer full generates an interrupt event. |
0 |
SPIx receive buffer full does not generate an interrupt event. |