15.4.1.1 High-Resolution Mode Data Registers

When High-Resolution mode is selected, some of the PWM Data registers have limited resolution. For some registers, the Least Significant bits (LSbs) of the data value are forced to ‘0’, regardless of the value written to the registers. When configuring the PWM in High-Resolution mode, first set the HREN bit before writing to data registers whose function is dependent on High-Resolution mode. High-resolution operational differences are summarized in Table 15-5.

Table 15-5. High-Resolution Mode PWM Data Registers
Register31:2019:1211:43210
PGxLEB(Note 5)0000
PGxPHASE
PGxDC
PGxDCA
PGxPER
PGxTRIGANote 1(Note 4)
PGxTRIGBNote 1(Note 4)
PGxTRIGCNote 10000
PGxTRIGDNote 10000
PGxTRIGENote 10000
PGxTRIGFNote 1(Note 4)
PGxDT
PGxCAP(Note 4)
FSCL(Note 3)
FSMINPER(Note 3)
MPHASE
MDC
MPER
Note:
  1. Bit[31] of the PGxTRIGx registers selects the counter phase that produces the trigger when operating in Center-Aligned modes.
  2. Bits[3:0] will read as ‘0’ in High and Standard-Resolution modes. Bit[0] is writable.
  3. Not used in High-Resolution mode.
  4. The 4 LSBs of the PGxTRIGA and PGxTRIGB will be used by the high-resolution circuitry when Dual PWM mode is selected and High-Resolution mode is enabled. When high resolution is enabled, these bits will be readable and writable. However, they will only be used by the Dual PWM feature.
  5. PGxLEB is a 20-bit register. The resolution of the PGxLEB register does not change in High-Resolution mode. PGxLEB[19:4] provides an adjustment of the blanking time in increments of TPWM with TPWM*5 being the minimum achievable blanking time when PGxLEB[19:4] ≤ 4.