15.4.1.2 High-Resolution Period Synchronization

When operating in High-Resolution mode, it is possible for PWM output edges to not be aligned with PGx_clk in which the rest of the PWM module operates. When PGxPER (or MPER) values are not divisible by eight, the period contains a fractional value of PGx_clk. This fractional clock difference can cause other events, including End-of-Cycle (EOC), triggers, etc. to not align with the output edges. The module contains an accumulator circuit to calculate and minimize the offset over long time periods.

If synchronous behavior is desired, it is recommended to use PGxPER values with bits[2:0] equal to ‘0’.

The fine edge placement circuit itself adds delay to the PWM outputs when compared to the base PWM signal. Using the base PWM signal for gating and synchronization in High-Resolution mode may cause unexpected results for a few fine edge clock cycles in some cases. For example, using the PCI’s auto-terminate feature will remove an override condition at EOC and place the PWM outputs back to their existing state. Override is applied after the fine edge placement circuit. Since the EOC event is based on the base PWM signal, the delay through the fine edge circuit may be observed before the next PWM cycle is started. This behavior can be mitigated by using a PHASE offset equal to PGxPER – 8. In addition to EOC events, using timers operating on the base PWM signal (such as LEB and PGxTRIGy) or other PWM Generators as a source may also be susceptible in some conditions.