15.5.1.1 Six-Step Commutation – PWM Scheme 1
In this PWM scheme, only two switches are active at any given time. Of the two active phases, one high-side and one low-side switch are controlled with their phase’s corresponding PWM waveform, as shown in Figure 15-41.
Since only one switch needs to be driven at a time on a given phase, Independent PWM Output mode is used. The output override feature is then used to suppress the unused output. A three-phase scheme is implemented using PWM Generator 1 (PG1) configured as a host and the other two PWM Generators (PG2 and PG3) configured as clients. PG1 is self-triggered, whereas PG2 and PG3 are triggered from PG1’s Start-of-Cycle (SOC). Enabling PG1 will start the system in a synchronized fashion.
Configuration Summary:
- Independent Edge PWM mode
- Independent Output mode
- Master period and Duty cycle used
- Override state is drive low.
Six-Step PWM Scheme 1 Code
#include <stdint.h>
//For delay function
#define FCY 8000000 //CPU frequency in Hz
#include "libpic30.h"
uint32_t state = 0;
uint32_t PWMState1[6] = {0x00100000,0x00100000,0x00300000,0x00200000,0x00200000,0x00300000};
uint32_t PWMState2[6] = {0x00200000,0x00300000,0x00100000,0x00100000,0x00300000,0x00200000};
uint32_t PWMState3[6] = {0x00300000,0x00200000,0x00200000,0x00300000,0x00100000,0x00100000};
void PWMInitialization(void);
int main(void)
{
PWMInitialization();
while (1)
{
for (state = 0; state < 6; state++)
{
/* Delay is used to simulate BLDC commutation; In practical
application, commutation state transition will be based on feedback from Motor */
__delay_us(200);
PG1IOCON2 = PWMState1[state];
PG2IOCON2 = PWMState2[state];
PG3IOCON2 = PWMState3[state];
}
}
}
void PWMInitialization(void)
{
PCLKCON = 0x0000;
//Set PWM master clock to 400MHz from PLL2 through CLKGEN5
configure_PLL2_Fout_400MHz();
clock_PWM_from_PLL2_Fout();
/* PWM Clock Divider Selection bits
0b11 = 1:16 ; 0b10 = 1:8 ;0b01 = 1:4 ; 0b00 = 1:2 */
PCLKCONbits.DIVSEL = 0;
/* PWM Master Clock Selection bits
0b01 = CLKGEN5 ; 0b00 = UPB clock */
PCLKCONbits.MCLKSEL = 1;
/* Lock bit: 0 = Write-protected registers and bits are unlocked */
PCLKCONbits.LOCK = 0;
/* Initialize Master Period Register */
MPER = 80000;
/* Initialize Master Duty Cycle */
MDC = 40000;
/* Initialize PG1CON Registers */
PG1CON = 0x00000000;
/*PWM Generator uses the master clock selected by the MCLKSEL[1:0]
* (PCLKCON[1:0] control bits */
PG1CONbits.CLKSEL = 1;
/* Select PWM Generator duty cycle register as MDC */
PG1CONbits.MDCSEL = 1;
/* Select PWM Generator period register as MPER */
PG1CONbits.MPERSEL = 1;
/* PWM Generator broadcasts software set of UPDREQ control bit and EOC signal
* to other PWM Generators. */
PG1CONbits.MSTEN = 1;
/* Start of cycle is local EOC */
PG1CONbits.SOCS = 0b0000;
/* PWM Generator operates in Independent Edge PWM mode*/
PG1CONbits.MODSEL = 0;
/* Initialize PG1IOCON Registers */
PG1IOCON1 = 0x00000000;
/* PWM Generator Output Mode is Independent Mode */
PG1IOCON1bits.PMOD = 1;
/* PWM Generator controls the PWMxH output pin */
PG1IOCON1bits.PENH = 1;
/* PWM Generator controls the PWMxL output pin */
PG1IOCON1bits.PENL = 1;
PG1EVT1 = 0x00000000;
/* A write of the PGxDC register automatically sets the UPDREQ bit */
PG1EVT1bits.UPDTRG = 0;
/* PWM generator trigger output is EOC*/
PG1EVT1bits.PGTRGSEL = 0;
/* Initialize PG2CON Registers */
PG2CON = 0x00000000;
/*PWM Generator uses the master clock selected by the MCLKSEL[1:0]
* (PCLKCON[1:0] control bits */
PG2CONbits.CLKSEL = 1;
/* Select PWM Generator Duty Cycle Register as MDC */
PG2CONbits.MDCSEL = 1;
/* Select PWM Generator Period Register as MPER */
PG2CONbits.MPERSEL = 1;
/* Start of Cycle is PG1 trigger output selected by
* PG1EV1Tbits.PGTRGSEL<2:0> bits */
PG2CONbits.SOCS = 0b0001;
/* PWM Generator operates in Independent Edge PWM mode*/
PG2CONbits.MODSEL = 0;
/* Initialize PG2IOCON Registers */
PG2IOCON1 = 0x00000000;
/* PWM Generator Output Mode is Independent Mode */
PG2IOCON1bits.PMOD = 1;
/* PWM Generator controls the PWMxH output pin */
PG2IOCON1bits.PENH = 1;
/* PWM Generator controls the PWMxL output pin */
PG2IOCON1bits.PENL = 1;
/* Initialize PG3CON Registers */
PG3CON = 0x00000000;
/*PWM Generator uses the master clock selected by the MCLKSEL[1:0]
* (PCLKCON[1:0] control bits */
PG3CONbits.CLKSEL = 1;
/* Select PWM Generator Duty Cycle Register as MDC */
PG3CONbits.MDCSEL = 1;
/* Select PWM Generator Period Register as MPER */
PG3CONbits.MPERSEL = 1;
/* Start of Cycle is PG1 trigger output selected by
* PG1EVT1bits.PGTRGSEL<2:0> bits */
PG3CONbits.SOCS = 0b0001;
/* PWM Generator operates in Independent Edge PWM mode*/
PG3CONbits.MODSEL = 0;
/* Initialize PG3IOCON Registers */
PG3IOCON1 = 0x00000000;
/* PWM Generator Output Mode is Independent Mode */
PG3IOCON1bits.PMOD = 1;
/* PWM Generator controls the PWMxH output pin */
PG3IOCON1bits.PENH = 1;
/* PWM Generator controls the PWMxL output pin */
PG3IOCON1bits.PENL = 1;
/* Enable PWM generator 3 */
PG3CONbits.ON =1;
/* Enable PWM generator 2 */
PG2CONbits.ON =1;
/* Enable PWM generator 1, starting all PWM generators together */
PG1CONbits.ON =1;
}