15.4.2.3 Clocking Synchronization

Due to the separate clocking domains of the PWM module and the CPU’s system clock, there are inherent synchronization delays associated with SFR reads. This delay is dependent on the relative speeds of the CPU (sys_clk) and the PWM Generator clock (PGx_clk). Typically, the CPU clock will be slower, and SFR data can be delayed up to one sys_clk cycle. It is also important to note that each PWM Generator can run at a different speed, and this can have an effect on interactions between PWM Generators.