15.4.2.1 Master Clocking

The PWM module provides several clocking features at the top level of the module. Each PWM Generator can then independently select one of the clock sources, as shown in Figure 1. The clock input into the PWM module is selected with the MCLKSEL control bit (PCLKCON[0]). The CLKSEL[1:0] control bits (PGxCON[4:3]) are used to select the clock for each PWM Generator instance; see PWM Generator Clocking for details. Frequency scaling and the clock divider are discussed in Shared Clocking. The CLKSELx bits need to be changed from the default selection to allow the PWM Generator to function.

Figure 15-4. PWM Generator Clocking

Note: Writing MCLKSEL to a non-zero value will request and enable the chosen clock source, whether any PWM Generators are enabled or not. This allows a PLL, for example, to be requested and warmed up before using it as a PWM clock source. For the lowest device power consumption, the MCLKSEL bits should be set to the value, ‘00’, if all PWM Generators have been disabled.

Changing the MCLKSEL or CLKSEL[1:0] bits while ON (PGxCON[15]) = 1) is not recommended.

Note: The CPU and PWM typically run at different clock speeds depending on the application requirements. If the PWM clock speed is equal or slower than the CPU, writes to registers may have delayed behavior. For example, if SWTERM is used to clear a Fault, the instruction may need to be stretched with a REPEAT instruction to ensure the PWM can detect the edge within its clock cycle.