34.2.9 DMT NMI Clear Register
Note:
- Bits[7:0] are also cleared when a DMT Reset event occurs. NMISTEP1 and NMISTEP2 are also cleared if NMISTEP2 is loaded with the correct value during the Pre-DMT Event Clear sequence.
| Name: | PPC |
| Offset: | 0x3A20 |
| Property: | R/W |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| NMISTEP2[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 7:0 – NMISTEP2[7:0] NMI Clear DMT Event Enable bits(1)
| Value | Description |
|---|---|
| 10001000b | If write pattern has been preceded by correct execution of PPPC NMI preclear instruction, the DMT event is cleared. |
| All other write patterns | This register remains unchanged and the instruction writing to it is considered to be unsuccessful. |