18.5.1 Peak Current-Mode Control

The SMPS topologies, such as Buck, Boost and Buck-Boost, generate subharmonic oscillations when controlled with Peak Current-mode control. These oscillations occur under specific conditions, such as Continuous Current mode and a duty cycle greater than 50%. The subharmonic oscillations can be damped by using slope compensation. The analog comparator module can be utilized for such applications, eliminating the need for additional external analog circuitry to perform slope compensation. The comparator module is used in conjunction with the PWM module to generate the Current-mode PWM signal. A typical Peak Current Buck mode power supply is illustrated in Figure 18-6.

The analog comparator module is configured to reset the PWM module when the measured inductor current peak reaches the current level determined by the outer control loop. The outer control loop consists of the output voltage, measured by the ADC, and compared with a desired voltage reference. The error counts generated are treated with a compensator gain to arrive at the peak current level for the current PWM cycle. The peak current level is applied to the DAC to generate an equivalent analog signal with which the actual inductor current is compared by the comparator. The waveforms of the Peak Current-mode control are as shown in Figure 18-7. Note that the pulse width is different in the consecutive cycles, even though the current reference, i_REF, is constant.

The slope compensation module alters the DAC output voltage slope, hence the reference to the inner current loop. In the absence of the slope compensation module, the output of the DAC is held constant for a given PWM cycle (as shown in Figure 18-8). The slope generation module causes the reference current to slope based on the values set in the register. The slope direction can be set to positive or negative depending on the applications, although negative slope is generally used. The rate of the slope is determined by the SLPxDAT register. DACDAT holds the DAC value at the start of the PWM cycle, and the DAC value at the end of the PWM cycle is held by DACLOW. The waveforms of the Peak Current-mode control with slope compensation are as shown in Figure 18-8. Note that the pulse width is the same in all cycles for a constant current reference, i_REF.

Initialize DAC with Slope Compensation shows the settings of the analog comparator module for generating the slope compensated waveforms. In this design, the buck converter operates at an input of 5V and an output of 3.3V, 1A. The operating frequency of the converter is 200 kHz. The period timer for the PWM is set at 200 kHz, and the duty cycle is set at 95%. The clock frequency for the DAC module is set at 500 MHz. The current measurement is connected to the positive input of the comparator. The DAC provides the reference current for the peak current trip and is connected internally to the negative input of the comparator. The reference current is generally the output of the compensator (digital filter), which operates on the outer voltage loop error signal. The PWM cycle is terminated when the measured input current exceeds the DAC reference current, i_REF, as shown by Point A in Figure 18-8. This is due to configuration of the SLPSTOPBx trigger in Figure 18-6.The dashed curve shows the reference current, i_REF, if SLPSTOPBx is not triggered. In this case, i_REF continues until the SLPSTOPAx signal is triggered and is indicated by Point B in Figure 18-8.

//PWM clock settings
    PCLKCONbits.MCLKSEL = 1;     //Use CLKGEN5 as PWM MCLK
    PG1CONbits.CLKSEL = 1;       //Use PWM Clock selected by MCLKSEL, undivided and unscaled
    
    //PWM clocking based on 200MHz MCLK from CLKGEN5. Each unit is 1/16 of an MCLK period.
    PG1PER = 1000 << 4;         // PWM frequency is 200 kHz, 5 uS period
    PG1DC = 950 << 4;           // 95% duty cycle, 4.75 uS on time 
    
    PG1IOCON1bits.PENH = 1;     // PWM Generator controls the PWMxH output pin
    PG1IOCON1bits.PENL = 1;     // PWM Generator controls the PWMxL output pin 
    
    // PWM PCI setup, use CLDAT when comparator 1 trips
    PG1CLPCI2 = 1 << 28;        // PCI source is Comparator 1 
    PG1CLPCI1bits.AQSS = 2;     // LEB active as Acceptance Qualifier 
    PG1CLPCI1bits.AQPS = 1;     // Invert Acceptance Qualifier (LEB not active)
    PG1CLPCI1bits.TERM = 1;     // Auto terminate as Termination Event
    PG1CLPCI1bits.ACP = 3;      // Latched PCI Acceptance Criteria
    PG1IOCON2bits.CLDAT = 0b01; // PWM1L = 1 and PWM1H = 0 if CL event is active
    PG1LEBbits.PHR = 1;         // Rising edge of PWMxH triggers the LEB counter
    
    PG1LEB = 100 << 4; // 500 nS LEB timer 
    
    // PWM to DAC Trigger setup 
    PG1TRIGA = 300 << 4;        // ADC Trigger 1 at 1.5 uS, used as SLPSTRT
    PG1EVT1bits.ADTR1EN1 = 1;   // PGxTRIGA as trigger source for ADC Trigger 1
    PG1TRIGB = 800 << 4;        // ADC Trigger 2 at 4 uS, used as SLPSTOPA
    PG1EVT2bits.ADTR2EN2 = 1;   // PGxTRIGB as trigger source for ADC Trigger 2
    PG1CONbits.ON = 1;          // Enable PWM
    
    // DAC Configuration
    DACCTRL2bits.SSTIME = 0x8A;   // Default value 552 nS @ 500MHz
    DACCTRL2bits.TMODTIME = 0x55; // Default value 340 nS @ 500MHz
    
    DAC1DATbits.DACDAT = 2703;    // 2.17v steady state value
    DAC1DATbits.DACLOW = 1113;    // 0.89v, value at the end slope
    
    
    DAC1SLPDATbits.SLPDAT = 41;   // Slope = (2703-1113)*16/((4u-1.5u)/4n)
    DAC1SLPCONbits.SLOPEN = 1;    // Enable Slope compensation 
    DAC1SLPCONbits.SLPSTRT = 1;   // PWM1 ADC Trigger 1
    DAC1SLPCONbits.SLPSTOPA = 1;  // PWM1 ADC Trigger 2
    DAC1SLPCONbits.SLPSTOPB = 1;  // Comparator 1
    DAC1CMPbits.CBE = 1;          // Enable comparator blanking
    DAC1CONbits.TMCB = 125;       // 125 * 4 nS = 500 nS blanking time
    DAC1CONbits.DACOEN = 1;       // Enable DAC output 
    DAC1CONbits.DACEN = 1;        // Enable DAC 1
    DACCTRL1bits.ON = 1;          // Enable DAC system