20.4.1.2 Fractional Division Mode

To reduce the baud rate error, a fractional division scheme can be used by setting CLKMOD = 1. The fractional baud clock circuit works by occasionally extending clock pulses of the 16x baud clock to achieve a baud clock closer to the ideal baud rate. This mode allows for faster operation of the UART while maintaining the noise rejection benefits of 16x oversampling, where in Legacy mode, a small value of BRG results in an unacceptable error.

The fractional Baud Rate Generation logic performs modulo arithmetic, where the value 16 is constantly accumulated in a counter until the sum is larger than the UxBRG register value. When the sum becomes larger than the UxBRG register value, a clock pulse is produced and the accumulated value is reduced by the value in the UxBRG register.

A timing example for the fractional baud clock circuit is shown in Figure 20-4. In this example, a 50 MHz UART clock and a target baud rate of 921600 baud are used. This results in UxBRG = 54. The upper waveform shows one full bit time, while the lower waveform shows the accumulation process. In this example, the 16x baud clock pulses are generated every three to four UART clock (F_UART) cycles. While this results in 16x baud clock sampling pulses with unequal periods, each full bit time (16 pulses of the 16x baud clock) will be equal. The resulting bit period generated will be closer to the ideal bit period than with the legacy divider-based BRG.

Equation 20-3 shows the baud rate formulas.

UART fractional baud rate setup procedure:

1. Select the clock input source with the CLKSEL[1:0] bits.
2. Set the CLKMOD bit.
3. Using Equation 20-3, calculate the value for BRG and write to the UxBRG register.
4. Set the ON bit.