Receive Errors and Events

The receive framing and parity errors are associated with each byte received. Frame and parity error flags, indicated by the FERIF and PERIF bits, will indicate only the error status of the last data byte received. As UxRXB is read, the flags indicate the status of the current (top) byte in the buffer. This behavior differs from prior UART modules.

If a byte is received when the receive buffer is full, the RXFOIF bit (UxSTAT[1]) will set. Setting the corresponding error interrupt enable will generate an error interrupt. To clear the RXFOIF bit, the receive buffer needs to be read at least once. This behavior differs from prior UART modules. The receiver can handle overflow conditions in one of two options, defined by the RUNOVF (UxCON[23]) bit. By default, when RUNOVF = 0, the receiver will stop receiving data when the RX buffer is full. Alternatively, when RUNOVF = 1, the receiver will continue to receive data and overwrite the contents of the RX shifter.

A line Idle condition (line high) is indicated by the RCIDL bit (UxSTAT[19]). The flag will clear when a Start bit is detected and a reception is in progress.