15.4.4.6 PWM Event Outputs
The PWM event output feature provides a mechanism to interface various PWM signals and events to other peripherals and external devices. The PWM event output logic provides a way to select and condition an event from any of the PWM Generators. Each PWM Event Output block has the following configuration options:
- PWM Generator Instance (PG1…PG8)
- Choice of Signal from PWM Generator
- Pulse Stretching
- Output Signal Polarity
- System Clock Synchronization
- Output Enable for the Signal
Each PWMEVTy register contains controls for a PWM event output. A device may have multiple instances (A-F) of the PWMEVTy registers, resulting in four or more total PWM event outputs.
The EVTySEL[3:0] (PWMEVTy[7:4]) bits select the signal to be used by the Output block. The default source is the selection determined by PGTRGSEL[2:0] (PGxEVT1[18:16]). For additional information on these signals and configuring the ADC triggers, see Event Selection Block. The EVTyPGS[2:0] bits (PWMEVTy[2:0]) are then used to select which of the eight PWM Generator’s event signals is to be used.
Some of the event signals running at high speed have short pulses that may not be detected by other circuits and would make it impossible, for example, to connect a PWM event signal to an off-chip destination. A pulse stretching circuit can be used to extend the duration of the pulse by setting the EVTySTRD bit (PWMEVTy[13]). If synchronization to the main PWM clock domain is desired, the EVTySYNC bit (PWMEVTy[12]) can be set. The EVTyPOL (PWMEVTy[14]) control is provided to invert the polarity of the event signal. Finally, an output enable bit, EVTyOEN (PWMEVTy[15]), is provided for control over the output pin PWMEy.
The PWM event output can also generate a system interrupt. An interrupt can be generated from any of the various triggers and events that are input into the Event Output block. A block diagram of the event output function is shown in Figure 15-39.