15.3.1.10 PWM Event Output Control Register y

Note: ‘y’ denotes a common instance (A-F).

Name:	PWMEVTy
Offset:	0x1038, 0x103C, 0x1040, 0x1044, 0x1048, 0x104C

Bit 15 – EVTyOEN PWM Event Output Enable bit

Value	Description
`1`	Event output signal is output on the PWMEy pin.
`0`	Event output signal is internal only.

Value	Description
`1`	Event output signal is active-low.
`0`	Event output signal is active-high.

Note: The event signal is stretched using peripheral_clk because different PWM Generators may be operating from different clock sources.

Value	Description
`1`	Event output signal pulse width is not stretched.
`0`	Event output signal is stretched to eight PWM clock cycles minimum.

Event output signal pulse will be synchronized to peripheral_clk.

Value	Description
`1`	Event output signal is synchronized to the system clock.
`0`	Event output is not synchronized to the system clock.

Note: This is the PWM Generator output signal prior to Output mode logic and any output override logic.

Value	Description
11111	FEP Calibration Error Event signal
11110	FEP Calibration Done Event signal
11101	FEP Lock Event signal
11100	FEP Lock Lost Event signal
11011	FEP Lock Time-Out Event signal
11010	FEP Runt Pulse Event signal
11001-01100	Reserved
01011	DAC Trigger signal
01010	ADC Trigger 2 signal
01001	ADC Trigger 1 signal
01000	STEER signal (available in Push-Pull Output modes only)
00111	PHASE signal (available in Center Aligned modes only)
00110	PCI Fault2 Active Output signal
00101	PCI Fault Active Output signal
00100	PCI Current Limit Active Output signal
00011	PCI Feed-Forward Active Output signal
00010	PCI Sync Active Output signal
00001	PWM Generator Output signal⁽¹⁾
00000	Source is selected by the PGTRGSEL[2:0] bits.