35.3.1.2.3 Delay on Wake-up from Sleep
Figure 35-1 shows the
wake-up delay from Sleep mode. This delay consists of the voltage regulator delay and
the oscillator delay:
- Voltage Regulator Delay: This is the time delay for the voltage regulator to transition from the Standby state to the Active state. This delay is required only if Standby mode is enabled for the voltage regulator.
- Oscillator Delay: The time delay for the clock to be ready for various clock sources is shown in Table 35-1. For details, refer to Oscillator Module.
Oscillator Source | Oscillator Start-up Delay | Oscillator Start-up Timer | PLL Lock Time | Total Delay |
---|---|---|---|---|
FRC, FRCDIV16, FRCDIVN | TOSCD | — | — | TOSCD |
FRCPLL | TOSCD | — | TLOCK | TOSCD + TLOCK |
XT | TOSCD | TOST | — | TOSCD + TOST |
HS | TOSCD | TOST | — | TOSCD + TOST |
EC | — | — | — | — |
XTPLL | TOSCD | TOST | TLOCK | TOSCD + TOST + TLOCK |
HSPLL | TOSCD | TOST | TLOCK | TOSCD + TOST + TLOCK |
ECPLL | — | — | TLOCK | TLOCK |
SOSC | TOSCD | TOST | — | TOSCD + TOST |
LPRC | TOSCD | — | — | TOSCD |
Note:
|
Note: Refer to Electrical Characteristics for TVREG,
TOST and TLOCK specifications and also for the
TOSCD specifications when using the internal FRC or internal LPRC
Oscillator.