35.3.1.2.3 Delay on Wake-up from Sleep

Figure 35-1 shows the wake-up delay from Sleep mode. This delay consists of the voltage regulator delay and the oscillator delay:
  • Voltage Regulator Delay: This is the time delay for the voltage regulator to transition from the Standby state to the Active state. This delay is required only if Standby mode is enabled for the voltage regulator.
  • Oscillator Delay: The time delay for the clock to be ready for various clock sources is shown in Table 35-1. For details, refer to Oscillator Module.
Figure 35-1. Wake-up Delay from Sleep Mode
Table 35-1. Oscillator Delay(1,2,3)
Oscillator SourceOscillator Start-up DelayOscillator Start-up TimerPLL Lock TimeTotal Delay
FRC, FRCDIV16, FRCDIVNTOSCDTOSCD
FRCPLLTOSCDTLOCKTOSCD + TLOCK
XTTOSCDTOSTTOSCD + TOST
HSTOSCDTOSTTOSCD + TOST
EC
XTPLLTOSCDTOSTTLOCKTOSCD + TOST + TLOCK
HSPLLTOSCDTOSTTLOCKTOSCD + TOST + TLOCK
ECPLLTLOCKTLOCK
SOSCTOSCDTOSTTOSCD + TOST
LPRCTOSCDTOSCD
Note:
  1. TOSCD = Oscillator start-up delay. Crystal oscillator start-up time varies with crystal characteristics, load capacitance, etc.
  2. TOST = Oscillator Start-up Timer delay.
  3. TLOCK = PLL lock time if PLL is enabled.
Note: Refer to Electrical Characteristics for TVREG, TOST and TLOCK specifications and also for the TOSCD specifications when using the internal FRC or internal LPRC Oscillator.