5.3.11 PWB ECC RAM Status Register

Note:
  1. This bit determines whether the PWBxECCEADDR, PWBxECCEDATA, PWBxECCVAL and PWBxECCSYND registers display information related to SEC or DED error events.
Table 5-12. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Gray cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
CWrite to clearSSoftware settable bitxChannel number
Name: PWBXECCSTAT, PWBYECCSTAT
Offset: 0x35A4, 0x35E4

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
    ESEL   PWBNE 
Access R/WR 
Reset 00 
Bit 76543210 
   SECOSEC  DEDODED 
Access R/C/HSR/C/HSR/C/HSR/C/HS 
Reset 0000 

Bit 12 – ESEL  Error Reporting Select bit(1)

ValueDescription
1Show SEC error event information
0Show DED error event information

Bit 8 – PWBNE Posted Write Buffer Not Empty Status bit

ValueDescription
1PWB has to perform at least one read or data merge or write operation, i.e., it is not empty
0PWB is empty; all data committed to RAM

Bit 5 – SECO Single Error Correction Event Overflow Status bit

ValueDescription
1SEC event not captured due to overflow
0No SEC event overflow detected

Bit 4 – SEC Single Error Correction Status bit

ValueDescription
1Single-bit error detected
0Single-bit error not detected

Bit 1 – DEDO Double Error Detection Event Overflow Status bit

ValueDescription
1DED event not captured due to overflow
0No DED event overflow detected

Bit 0 – DED Double Error Detection Indicator Status bit

ValueDescription
1Double-bit error detected
0Double-bit error not detected