5.3.9 PWB ECC RAM Control Register

Note:

This bit can be set by software, but not cleared. It is cleared by any device Reset.

Table 5-10. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Gray cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
C	Write to clear	S	Software settable bit	x	Channel number

Name:	PWBXECCCON, PWBYECCCON
Offset:	0x35A0, 0x35E0


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8
	ON
Access	R/S
Reset	0


Bit	7	6	5	4	3	2	1	0
								FLTINJ
Access								R/W
Reset								0

Bit 15 – ON Enable ECC functionality.⁽¹⁾

By default, the ECC is disabled on device Reset. It is the software responsibility to initialize the RAM locations with valid data, then set this bit to “1”.

Value	Description
`1`	ECC is enabled
`0`	ECC is disabled

Bit 0 – FLTINJ Fault Injection Enable bit

Value	Description
`1`	Fault injection is enabled when the read address of Data RAM[23:2] matches with PWBxECCFADDR[23:2]
`0`	Fault injection is disabled

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