5.3.13 PWB ECC RAM Error Address Register

Table 5-14. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Gray cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
C	Write to clear	S	Software settable bit	x	Channel number

Name:	PWBXECCEADDR, PWBYECCEADDR
Offset:	0x35B0, 0x35D0


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16
	ADDR[23:16]
Access	R/HS/HC	R/HS/HC	R/HS/HC	R/HS/HC	R/HS/HC	R/HS/HC	R/HS/HC	R/HS/HC
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	ADDR[15:8]
Access	R/HS/HC	R/HS/HC	R/HS/HC	R/HS/HC	R/HS/HC	R/HS/HC	R/HS/HC	R/HS/HC
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	ADDR[7:2]
Access	R/HS/HC	R/HS/HC	R/HS/HC	R/HS/HC	R/HS/HC	R/HS/HC
Reset	0	0	0	0	0	0

Bits 23:16 – ADDR[23:16]

Bits 15:8 – ADDR[15:8]

Bits 7:2 – ADDR[7:2] ECC RAM Read Data Address bits

These bits represent the faulty memory location when Single-bit (SEC) or Double-bit (DED) ECC errors occur. The values of these register bits represent the relative address from the start address of the X or Y data spaces, depending on the instance of this register. To determine the corresponding system bus address, the start address should be added to this relative address.