5.3.12 PWB ECC RAM Fault Injection Address Register

Table 5-13. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Gray cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
C	Write to clear	S	Software settable bit	x	Channel number

Name:	PWBXECCFADDR, PWBYECCFADDR
Offset:	0x35AC, 0x35EC


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16
	ADDR[23:16]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	ADDR[15:8]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	ADDR[7:2]
Access	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0

Bits 23:16 – ADDR[23:16]

Bits 15:8 – ADDR[15:8]

Bits 7:2 – ADDR[7:2] ECC Fault Injection Address bits

These register bits are compared against the RAM address read during the Fault injection cycle.

These register bits’ values represent the relative address from the start address of X or Y data spaces depending on the instance of this register. The start address should be added to this relative address to determine the corresponding data RAM address.