5.3.7 RAM ECC Value Register

Table 5-8. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Gray cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
C	Write to clear	S	Software settable bit	x	Channel number

Name:	RAMXECCVAL, RAMYECCVAL
Offset:	0x3598, 0x35D8

Bits 6:0 – ECC[6:0] Error Correcting Code bits

These bits register the Error Correcting Code associated with the RAM read data when Single or Double-bit ECC errors occur.