5.3.10 PWB ECC RAM Fault Pointer Register

Table 5-11. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Gray cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
C	Write to clear	S	Software settable bit	x	Channel number

Name:	PWBXECCFPTR, PWBYECCFPTR
Offset:	0x35A8, 0x35E8


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8
			FLT2LPTR[5:0]
Access			R/W	R/W	R/W	R/W	R/W	R/W
Reset			0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
			FLT1LPTR[5:0]
Access			R/W	R/W	R/W	R/W	R/W	R/W
Reset			0	0	0	0	0	0

Bits 13:8 – FLT2LPTR[5:0] ECC Fault Injection Bit Pointer 2

Value	Description
`111111-100111`	No Fault injection
`100110`	Fault injection (bit inversion) occurs on bit 38 of ECC bit order
...
000001	Fault injection (bit inversion) occurs on bit 1 of ECC bit order
000000	Fault injection (bit inversion) occurs on bit 0 of ECC bit order

Bits 5:0 – FLT1LPTR[5:0] ECC Fault Injection Bit Pointer 1

Value	Description
`111111-100111`	No Fault injection
`100110`	Fault injection (bit inversion) occurs on bit 38 of ECC bit order
...
000001	Fault injection (bit inversion) occurs on bit 1 of ECC bit order
000000	Fault injection (bit inversion) occurs on bit 0 of ECC bit order

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