13.4.3.1 SPI Control Register (CONTROL)
The following table provides details about the SPI Control register. Using this register, the SPI mode (Master/Slave), the type of the protocol it uses, and the data frame count can be set.
| Bit Number | Name | R/W | Reset Value | Description |
|---|---|---|---|---|
| 31 | RESET | R/W | 1 | 0: SPI is enabled. 1: SPI is held in Power reset state. |
| 30 | OENOFF | R/W | 0 | 0: SPI output enable active as required. 1: SPI output enable is not asserted. Allows multiple slaves to share a single slave select signal with a single master. |
| 29 | BIGFIFO | R/W | 0 | Alters FIFO depth when frame size is [4-8] bits. 0: FIFO depth is 4 frames. 1: FIFO depth is 32 frames when frame size is [9-16] bits FIFO depth is 16; and when frame size is [17-32] bits FIFO depth is 8. |
| 28 | CLKMODE | R/W | 0 | Specifies the methodology used to calculate the SPICLK divider. 0: SPICLK = 1 / (2CLK_GEN + 1) where CLK_GEN = 0 to 15. 1: SPICLK = 1 / (2 × (CLK_GEN + 1)) where CLK_GEN = 0 to 255. |
| 27 | FRAMEURUN | R/W | 0 | 0: The under-runs are generated whenever a
read is attempted from an empty transmit FIFO. 1: The under-run condition is ignored for the complete frame, if the first data frame read resulted in a potential overflow; that is, the slave was not ready to transmit any data. If the first data frame is read from the FIFO and transmitted, an under-run is generated, when the FIFO becomes empty for any of the remaining packet frames (that is, while SSEL is active). Master operation does not create a transmit FIFO under-run condition. |
| 26 | SPS | R/W | 0 | Defines slave select behavior. See Table 13-3. |
| 25 | SPH | R/W | 0 | Clock phase |
| 24 | SPO | R/W | 0 | Clock polarity |
| [23:8] | TXRXDFCOUNT | R/W | 0001 | Number of data frames to be sent or received. Counts from 1. Maximum value is 0XFFFF. |
| 7 | INTTXTURUN | R/W | 0 | Interrupt on transmit the under-run 0: Interrupt disabled 1: Interrupt enabled |
| 6 | INTRXOVRFLO | R/W | 0 | Interrupt on receive overflow 0: Interrupt disable 1: Interrupt enabled |
| 5 | INTTXDATA | R/W | 0 | Interrupt on transmit data 0: Interrupt disabled 1: Interrupt enabled |
| 4 | INTRXDATA | R/W | 0 | Interrupt on receive data 0: Interrupt disabled 1: Interrupt enabled |
| [3:2] | TRANSFPRTL | R/W | 0 | Transfer protocol Decode: 0b00: Motorola SPI 0b01: TI synchronous serial 0b10: National Semiconductor MICROWIRE 0b11: Reserved The transfer protocol cannot be changed while the SPI is enabled. |
| 1 | MODE | R/W | 1 | SPI implementation 0: Slave 1: Master (default) |
| 0 | ENABLE | R/W | 0 | Core enable 0: Disable (default) 1: Enable The core does not respond to external signals (SPI_X_DI, SPI_X_DO) until this bit is enabled. SPI_X_CLK is driven low and SPI_X_DOE_N and SPI_X_SS (slave select) are driven inactive. |