3.2.5 Interfaces

The following figure shows the Cache Controller interface in the MSS subsystem. There are two interfaces through which the Cache Controller is connected to the main memories:

Interface towards MDDR bridge: 128-bit AHB-Lite, this interface is read-only for instruction/data reads and 32-bit AHB-Lite to access DDR memory through DDR bridge and system bus (read and write access)

Interface towards AHB bus matrix: There are three 32-bit AHB-Lite modes:

  • Read/write for non-cacheable data access to eSRAM/eNVM
  • Read/write from SBus
  • Read/write from ICode bus
Figure 3-6. Cache Controller Interface