3.2.1 Cache Matrix

The cache matrix is a multi-layer AHB-Lite switch matrix. It takes care of the connectivity between masters and slaves, arbitration for slaves, memory mapping between main memory (eNVM, eSRAM, or DDR), and Cache Memory. The masters and slaves in the AHB matrix are referred to as mirrored masters (MM) and mirrored slaves (MS).

One master can access a slave at the same time another master accesses another slave. If more than one master attempts to access the same slave simultaneously, arbitration is performed. Each of the slave devices contains an arbiter, which manages accesses when more than one master attempts to access a slave at the same time.