3.2.3 Memory Maps and Transaction Mapping

The following table depicting transaction mapping depends upon the Memory map mode selected and the possible destination slave for the transaction.

For example, the case eNVM Remapped mode is selected—the condition mentioned in the first row in the table—If the cacheable transaction comes on ICode bus it will be targeted for the eNVM. This transaction initiates on mirrored slave 2 (MS2). The transaction flow will be (MS4 – MM3 – MS2) and it will be routed through AHB Bus Matrix. As shown in the Figure 3-2, all the instruction fetch are first checked in the Cache Engine that is MS4 and from there to Cache Memory. If not present, then as shown in the following table, the corresponding routing slave will be selected (For eNVM Remap mode it is switch MS2). The following are the abbreviations used in the table:

IC: Instruction CODE (ICODE) Cacheable

INC: ICODE Non Cacheable

NC: Non Cacheable

DC: Data CODE (DCODE) Cacheable

DNC: DCODE Non Cacheable

(W): Write

(R): Read

Table 3-4. Data Path for Various Maps
#	Memory Map Mode	Buses	Supported Trans	Region	Destination Slave	Routed Through
1	Default Memory Map - eNVM Remapped
		ICODE	IC	eNVM	MS2	AHB Bus Matrix
			INC	eNVM	MS2	AHB Bus Matrix
		DCODE	DC	eNVM	MS2	AHB Bus Matrix
			DNC	eNVM	MS0	AHB Bus Matrix
		System Bus	NC	DDR	MS5	MSS DDR Bridge
			NC	NON DDR	MS1	AHB Bus Matrix
		System Controller Bus	NC	DDR	MS5	MSS DDR Bridge
			NC	NON DDR	MS1	AHB Bus Matrix
2	eSRAM Remapped
		ICODE	INC	eNVM	MS2	AHB Bus Matrix
			INC	DDR	MS3	MSS DDR Bridge
			INC	eSRAM	MS2	AHB Bus Matrix
		DCODE	DNC	eNVM	MS0	AHB Bus Matrix
			DNC (R)	DDR	MS3	MSS DDR Bridge
			DNC (W)	DDR	MS5	MSS DDR Bridge
			DNC	eSRAM	MS0	AHB Bus Matrix
		SBUS	NC	DDR	MS5	MSS DDR Bridge
			NC	NON DDR	MS1	AHB Bus Matrix
		GBUS	NC	DDR	MS5	MSS DDR Bridge
			NC	NON DDR	MS1	AHB Bus Matrix
3	DDR Remapped
		ICODE	IC	DDR	MS3	MSS DDR Bridge
			INC	DDR	MS3	MSS DDR Bridge
		DCODE	DC	DDR	MS3	MSS DDR Bridge
			DNC(R)	DDR	MS3	MSS DDR Bridge
			DNC(W)	DDR	MS5	MSS DDR Bridge
		SBUS	NC	DDR	MS5	MSS DDR Bridge
			NC	NON DDR	MS1	AHB Bus Matrix
		GBUS	NC	DDR	MS5	MSS DDR Bridge
			NC	NON DDR	MS1	AHB Bus Matrix