13.2.2.5 Texas Instruments Synchronous Serial Protocol

The Texas Instruments (TI) synchronous serial interface is based on a full-duplex, four-wire synchronous transfer protocol. The transmit data pin is put in a high-impedance mode (tristated) when no data is transmitted.

• The slave select (SPI_X_SS[x]) signal is pulsed between transfers to guarantee a high-to-low transition between each frame.
• The slave select output polarity is inverted to become active-high. In an idle state, the slave select (SPI_X_SS[x]) signal is kept low.
• Data is available on the clock cycle immediately following the slave select (SPI_X_SS[x]) assertion.
• Both the SPI master and the SPI slave capture each data bit into their serial shift registers on the falling edge of the clock (SPI_X_CLK). The received data is latched on the rising edge of the clock (SPI_X_CLK).
• The output enable signal (SPI_X_DOE_N) is asserted (active Low) throughout the transfer.

The following figures show the TI synchronous single frame transfer and TI synchronous multiple frame transfer.