13.2.2.6 Slave Protocol Engine

The Slave Protocol Engine (SPE) implements a Microchip-defined hardware protocol that allows the transfer of command and data from an SPI master to the SPI slave. The SPE controller logically sits between the SPI transmit/receive logic and FIFOs. The SPE controller removes the command bytes and inserts status bytes from the data stream. Only one command byte is defined by Microchip (POLL command). All other command bytes are user defined. To use the SPE, the BIGFIFO, AUTOSTATUS, AUTOPOLL, FRAMEURUN, and SPS bits should be set (see the SPI Table 13-9 register for bit definitions). The following descriptions assume that the frame size (Table 13-10[TXRXDFS] field) is set to 8 bits, although, other frame size settings are acceptable (up to 32 bits).