7.4.1.23 HPDMA Debug Register
| Bit Number | Name | Reset Value | Description |
|---|---|---|---|
| 0 | HPDMADR_BFR_EMPTY | 1 | Data buffer is empty; HPDMA controller initiates idle transfers on the destination memory end. 1: Data buffer is empty. 0: Data Buffer is not empty. |
| 1 | HPDMADR_BFR_FULL | 0 | Data buffer is full; HPDMA controller initiates idle transfers on the source memory end. 1: Data buffer is full. 0: Data buffer is not full. |
| 4:2 | HPDMADR_BFR_RD_PNTR[2:0] | 0 | HPDMA data buffer read pointer |
| 7:5 | HPDMADR_BFR_WR_PNTR[2:0] | 0 | HPDMA data buffer write pointer |
| 11:8 | HPDMADR_AHM1_CST_DBG[3:0] | 0 | Master 1 (AHB bus matrix) current state 0001 – IDLE 0010 – WRITE 0100 – READ 1000 – WAIT |
| 15:12 | HPDMADR_AHM2_CST_DBG[3:0] | 0 | Master 2 (MSS DDR bridge) current state 0001 – IDLE 0010 – WRITE 0100 – READ 1000 – WAIT |
| 18:16 | HPDMADR_WBC_CST_DBG[2:0] | 0 | Write buffer controller current state 001 – IDLE 010 – RUN 100 – WAIT |
| 21:19 | HPDMADR_RBC_CST_DBG[2:0] | 0 | Read buffer controller current state 001 – IDLE 010 – RUN 100 – WAIT |
| 25:22 | HPDMADR_RRBN_CST_DBG[3:0] | 0 | Round robin FSM current state 0001 – D0 0010 – D1 0100 – D2 1000 – D3 |
| 27:26 | HPDMADR_DMA_CST_DBG[1:0] | 0 | DMA controller FSM current state 01 – IDLE 10 – RUN |
| 31:28 | Reserved | 0 | Software must not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit must be preserved across a read-modify-write operation. |