21.5.19 Software Reset Control Register
| Bit Number | Name | Reset Value | Description |
|---|---|---|---|
| [31:27] | Reserved | 0 | |
| 26 | MDDR_DDRFIC_SOFTRESET | 0x1 | 0: Releases DDR_FIC controller from reset 1: Keeps DDR_FIC controller in reset |
| 25 | MDDR_CTLR_SOFTRESET | 0x1 | 0: Releases MDDR controller from reset 1: Keeps MMDR controller in reset |
| 24 | MSS_GPOUT_31_24_SOFTRESET | 0x1 | 0: Releases GPIO_OUT[31:24] from reset 1: Keeps GPIO_OUT[31:24] in reset |
| 23 | MSS_GPOUT_23_16_SOFTRESET | 0x1 | 0: Releases GPIO_OUT[23:16] from reset 1: Keeps GPIO_OUT[23:16] in reset |
| 22 | MSS_GPOUT_15_8_SOFTRESET | 0x1 | 0: Releases GPIO_OUT[15:8] from reset 1: Keeps GPIO_OUT[15:8] in reset |
| 21 | MSS_GPOUT_7_0_SOFTRESET | 0x1 | 0: Releases GPIO_OUT[7:0] from reset 1: Keeps GPIO_OUT[7:0] in reset |
| 20 | MSS_GPIO_SOFTRESET | 0x1 | 0: Releases the GPIO from reset, as long as it isn’t being held in reset by some other means 1: Keeps the GPIO to be held in reset Asserting this soft reset bit holds APB register, GPIO input, and interrupt generation logic. This reset does not affect the GPIO OUT logic |
| 19 | FIC_1_SOFTRESET | 0x1 | 0: Releases FIC _1 from reset 1: Keeps FIC_1 in reset |
| 18 | FIC_0_SOFTRESET | 0x1 | 0: Releases FIC _0from reset 1: Keeps FIC_0 in reset |
| 17 | HPDMA_SOFTRESET | 0x1 | 0: Releases HPDMA from reset 1: Keeps HPDMA n reset |
| 16 | FPGA_SOFTRESET | 0x1 | 0: Releases FPGA from reset. This bit controls the MSS_RESET_N_M2F signal to release the FPGA from reset. 1: Keeps FPGA in reset |
| 15 | COMBLK_SOFTRESET | 0 | 0: Releases COMM_BLK from reset 1: Keeps COMMUNICATION BLOCK (COMM_BLK) in reset |
| 14 | USB_SOFTRESET | 0x1 | 0: Releases USB from reset 1: Keeps USB in reset |
| 13 | CAN_SOFTRESET | 0x1 | 0: Releases CAN from reset 1: Keeps CAN in reset |
| 12 | I2C1_SOFTRESET | 0x1 | 0: Releases I2C_1 from reset 1: Keeps I2C_1 in reset |
| 11 | I2C0_SOFTRESET | 0x1 | 0: Releases I2C_0 from reset 1: Keeps I2C_0 in reset |
| 10 | SPI1_SOFTRESET | 0x1 | 0: Releases SPI1 from reset 1: Keeps SPI1 in reset |
| 9 | SPI0_SOFTRESET | 0x1 | 0: Releases SPI0 from reset 1: Keeps SPI0in reset |
| 8 | MMUART1_SOFTRESET | 0x1 | 0: Releases MMUART_1 from reset 1: Keeps MMUART_1 in reset |
| 7 | MMUART0_SOFTRESET | 0x1 | 0: Releases MMUART_0 from reset 1: Keeps MMUART_0 in reset |
| 6 | TIMER_SOFTRESET | 0x1 | 0: Releases the system timer from reset 1: Keeps the system timer in reset |
| 5 | PDMA_SOFTRESET | 0x1 | 0: Releases the PDMA from reset 1: Keeps the PDMA in reset |
| 4 | MAC_SOFTRESET | 0x1 | 0: Releases the Ethernet MAC from reset 1: Keeps the Ethernet MAC in reset |
| 3 | ESRAM1_SOFTRESET | 0 | 0: Releases the eSRAM_1 memory controller from reset 1: Keeps the eSRAM_1 memory controller in reset |
| 2 | ESRAM0_SOFTRESET | 0 | 0: Releases the eSRAM_0 memory controller from reset 1: Keeps the eSRAM_0 memory controller in reset |
| 1 | ENVM1_SOFTRESET | 0 | 0: Releases the eNVM_1memory controller from reset 1: Keeps the eNVM_1 memory controller in reset |
| 0 | ENVM0_SOFTRESET | 0 | 0: Releases the eNVM_0 memory controller from reset 1: Keeps the eNVM_0 memory controller in reset |
Reset values in the preceding table are the default values of the bits when peripherals are not configured using the software. If the peripheral is enabled using the software then the default reset value for that bit is 0x0.
Important: Do not change these register fields dynamically for
005 and 010 devices, see 21.5.1 System Registers Behavior for M2S005/010 Devices.