19.2.3.2.1 Cortex-M3 Processor in Debug State

The halted output from the Cortex-M3 is asserted when the processor is in debug mode and this signal is fed to the Watchdog. When the halted signal is asserted, the watchdog timer counter is halted. This ensures that the watchdog timer timeout-related resets or interrupts do not occur when a system debug session is in progress.