8.2.3.3 Interrupt

To use PDMA interrupt to Cortex-M3, Bit 8 of INTERRUPT_ENABLE0 register (located at address 0x40006000) has to be set. The PDMA Interrupt signal is also mapped to the dedicated interrupt signal MSS_INT_M2F[8] of the fabric interface interrupt controller (FIIC). This is to interrupt the user logic instantiated in the FPGA.

To determine transfer complete interrupt for each channel, the BUFFER_STATUS_x register bits[1:0] has to be monitored. The bit 7 and bit 8 of CHANNEL_x_CONTROL register are used to clear the transfer complete interrupts of the channel.